Parallel Computer Architecture

5.1 Cache Coherence

273

hardware primitives

on

cache-coherent multiprocessors

and how

algorithms

for

locks

and

barriers

can be

tailored

to use the

machine efficiently Section

5.6

dis-

cusses

the

implications

for

parallel programming

in

general,

and in

particular,

it

discusses

how

temporal

and

spatial data locality

may be

exploited

to

reduce cache

misses

and

traffic

on the

shared bus.

CACHE COHERENCE

Think

for a

moment about your intuitive model

of

what

a

memory should

do. It

should provide

a set of

locations that hold values,

and

when

a

location

is

read

it

should return

the

latest value written

to

that location. This

is the

fundamental prop