Parallel Computer Architecture

7.5 Dedicated Message Processing 501

chip FIFOs are uncached and must be done one double word (64 bits) at a time. The

first word of a message must contain the route (X-Y displacements in a 2D mesh),

but the hardware does not impose any other restriction on the message format. In

particular, it does not distinguish between system and user messages. In addition, the

NI chip also performs parity and CRC checks to maintain end-to-end data integrity

Two DMA engines, one for sending and the other for receiving, can transfer a

contiguous block of data between main memory and the NI chip at 400MB/s. The

memory region is specified as a physical address ...