September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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466
CHAPTER
7 Scalable Multiprocessors
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FIGURE 7.5 CM-5 machine organization. Each node is a repackaged SparcStation chip set (proces-
sor, FPU, MMU, cache, memory controller, and DRAM) with a network interface chip on the MBUS. The
networks (data, control, and diagnostics) form
a
"scalable backplane" connecting
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