Parallel Computer Architecture

xxvi Preface

multiprocessor systems without impeding performance. The techniques exploit two

basic capabilities: overlapping latency with useful work and pipelining the transfer

of data. The simplest of these techniques are essentially bulk transfers, which pipe-

line the movement of a large regular sequence of data items and often can be

off-

loaded from the processor. The other techniques attempt to hide the latency

incurred in collections of individual loads and stores. Write latencies are hidden by

exploiting weak consistency models, which recognize that ordering is conveyed by

only a small set of the accesses to shared memory in a program ...