Parallel Computer Architecture

5.4 Assessing Protocol Design Trade-offs 315

 Address bus

Data bus

FIGURE 5.19 Per-processor bandwidth requirements for the various applications,

assuming 200-MIPS/MFLOPS processors and 64-KB caches. The traffic

is.

split into data

traffic and address (including command) bus traffic. The leftmost bar shows traffic for the

Illinois MESI protocol, the middle bar for the case where we use the basic three-state invali-

dation protocol without the

E

state (as described in Section 5.3.1), and the rightmost bar for

the three-state protocol when we use BusRdX instead of BusUpgr for

S

-> M transitions.

are two types: true sharing and false sharing misses ...