September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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344 CHAPTER 5 Shared Memory Multiprocessors
In the test-and-test&set lock, since a test&set operation (and hence a bus trans-
action) is only issued when a processor is notified that the lock is ready, and there-
after if it fails it busy-waits (spins) on a cached block, there is no need for
backoff.
However, the lock does have the problem that when the lock is released, all waiting
processes rush out and perform their read misses and their test&set instructions at
about the same time. The bus transactions for the read misses may be combined in a
smart bus protocol; however, each of the test&set instructions itself generates inval-
idations an ...
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