Parallel Computer Architecture

11.7 Multithreading in a Shared Address Space 911

Thread

A

Thread

B

Thread

C

Thread

D

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I I UNI fil

S

D

Busy cycles from

threads

A-D

t

respectively

Overhead

of

making

threads unready due

to

squashing instructions

Idle (stall) cycle

Memory latency

\A~

~D

FIGURE

11.30

Latency tolerance

In the

interleaved scheme.

A

four-stage pipeline

is

assumed,

the stages being instruction fetch (IF), decode (D), execute (E), and write back (WB). The top part

of

the

figure shows how the four active threads on

a

processor would behave

if

each was the only thread

run-

ning

on the

processor.

The

bottom part shows

how the

processor switches amon ...