September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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408 CHAPTER 6 Snoop-Based Multiprocessor Design
A simple way to follow the first approach is to ensure that all incoming transac-
tions from the bus (invalidations, read-miss replies, write commitment acknowledg-
ments, etc.) propagate to the processor in FIFO order. However, such strict ordering
is not necessary. Consider preserving the desirable property just described with an
invalidation-based protocol. Here, there are two ways for a new value to be brought
into the cache and made available to the processor to read without it incurring
another bus operation. One is through a read miss, and the other is through a write
by that processor. O ...
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