September 1998
Intermediate to advanced
1056 pages
55h 28m
English
Content preview from Parallel Computer Architecture
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5.4 Assessing Protocol Design Trade-offs 305
Processor Action State in ?
ë
State in P
2
State in P
3
Bus Action Data Supplied By
1.
2.
3.
4.
5.
Pi
p
3
p
3
Pi
p
2
reads u
reads u
writes u
reads u
reads u
E
Sc
Sc
Sc
Sc
SC
-
Sc
Sm
Sm
Sm
BusRd
BusRd
BusUpd
null
BusRd
Memory
Memory
P
3
cache
-
P
3
cache
FIGURE 5.17 The Dragon update protocol in action for the processor actions shown in
Figure 53- The figure shows the state of the relevant memory block at the end of each processor
action,
the bus transaction generated (if any), and the entity supplying the data.
atomic bus, a lot like they were in the write-through case. However, with both
invalidation- an ...
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