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(i.e., a hard macro), a parameterizable component to meet design requirements
(i.e., a soft macro), or a custom-designed computational block to meet the per-
formance, power, and other design constraints. The architectural landscape for
these computational IP blocks range from off-the-shelf general purpose proces-
sor (GPP) cores, through application-specifi c instruction-set processors (ASIPs),
reconfi gurable cores (RCs), and custom-designed application-specifi c integrated
circuit (ASIC) blocks. In going from a GPP to an ASIC block, the system designer is
typically trading off fl exibility (general purpose programmability) vs. performance,