On-Chip Communication Architectures

12 CHAPTER 1 Introduction

This indicates that communication, and not computation, will be the key perfor-

mance bottleneck in DSM technologies. In addition, total wire length on a chip is

expected to amount to 2.22 km/cm

2

by the year 2010 ( Fig. 1.7 ) [4]. Another obser-

vation is the increase of power dissipation due to the charging and discharging of

interconnection wires on a chip. According to [4,5], the capacitance portion of the

interconnect contributes to about 30% of the total capacitance of a chip, and soon

the interconnect will consume about 50 times more power than logic circuits [6].

This means that for MPSoC designs in the DSM er ...