July 2010
Intermediate to advanced
544 pages
22h 33m
English
Content preview from On-Chip Communication Architectures
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transfers, freeing up processors for more useful work. Besides these master cores,
the application also has a number of memory blocks, network interfaces, and
peripherals such as interrupt controllers ( ITC1, ITC2), timers ( Watchdog, Timer1,
Timer2), universal asynchronous receiver/transmitters, UARTs ( UART1, UART2 ),
and data packet accelerators ( ASIC1, ASIC2 ).
Figure 6.22 shows the power-performance trade-off graph obtained from
the output solution set using the methodology from [50], for the MPSoC appli-
cation. The x-axis shows solutions in the output set having different number of
buses, while the y-axis shows the percentage ...
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