On-Chip Communication Architectures

196 CHAPTER 6 Synthesis of On-Chip Communication Architectures

[24] was to obtain a solution with minimum wire energy, Guo et al. [25] proposed

generating a set of solutions to trade-off chip area, energy, and delay. An SA-based

approach for synthesizing a cascaded bus matrix was presented by Yoo et al. [26].

6.2 BUS PROTOCOL PARAMETER SYNTHESIS

In addition to their topology, bus-based communication architectures are charac-

terized by several protocol parameters, such as bus widths, bus clock frequencies,

transaction burst sizes, arbitration schemes, and buffer sizes. These parameter val-

ues can have a signifi cant impact on the performance, ...