On-Chip Communication Architectures

33

(described in more detail in Chapter 4). Finally, additional bus logic must also be

added (to the arbiter module, or separately) to ensure that data transfer ordering

is maintained, for transfers originating from multiple masters.

2.3.6 Broadcast Transfer

Typically, data transfers on the bus involve just two components—a master and

a slave. Appropriate select signals ensure that only the source and destination

components sample data onto and off the bus. However, it is possible for the data

on the bus to be “ visible ” to other components on the bus, besides the two that

are involved in the transfer. This is because every time a data ...