On-Chip Communication Architectures

192 CHAPTER 6 Synthesis of On-Chip Communication Architectures

initial single shared bus architecture for the Sobel SoC that violates latency con-

straints. On applying the heuristic to the example, the SRAM, LCD registers, HW

registers, and APB (advanced peripheral bus) bridge become the private slaves of

the ARM processor master, while the ARM and LCD controller master interfaces

are grouped together, as shown in Fig. 6.3(b) . The resulting architecture meets

latency constraints and is estimated to consume 29.6% less power compared to

the single layer architecture. The output of applying the heuristic on the vector

quantization SoC (system-on-chip) ...