On-Chip Communication Architectures

54 CHAPTER 3 On-Chip Communication Architecture Standards

that it connects every master to every slave in the system, resulting in a very large

number of buses (and consequently wires and bus logic components). Such a

confi guration, therefore, achieves high performance at the cost of high power con-

sumption and a larger area footprint. For systems that have less stringent perfor-

mance requirements, a partial AHB bus matrix [8, 9] topology can be used. Figure

3.11(b) shows a partial AHB bus matrix confi guration that clusters components

onto shared buses, to reduce the number of buses in the matrix. This partial matrix

confi guration offers less ...