On-Chip Communication Architectures

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are unable to account for non-deterministic traffi c generation by the compo-

nents on the buses, and consequently cannot predict dynamic component (e.g.,

memory access) delays. These static approaches also cannot accurately account

for other sources of dynamic delays such as those arising due to complex arbitra-

tion and traffi c congestion, cache misses, burst interruptions, interface buffer over-

fl ows, and the effect of advanced bus features such as SPLIT transactions [10] and

out-of-order (OO) transaction completion [12]. Often, static techniques tend to

assume that computation and communication in a system can be statically sched-

uled,