On-Chip Communication Architectures

6 CHAPTER 1 Introduction

the computation blocks and the communication architecture is also refi ned to a

pin-accurate level, with all the signals needed for communication being explic-

itly modeled. These steps lead to the creation of a detailed implementation

model. This model is essentially an RTL model, which can be an input to standard

logic synthesis tools to create a gate level netlist of the design. Subsequently, the

designer performs placement of the various modules on the chip fl oor plan, fol-

lowed by a routing step to connect the modules together. The resulting GDSII fi le

is then handed to a semiconductor foundry for fabricating the MPSoC ...