On-Chip Communication Architectures

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used to implement required features of the selected protocols such as memory

and glue logic synchronization circuits. The channel delay model is given by:

tkt t mt t

i

i

i

i

p

C

SW FPGA, DPR WIRE,

    

∑∑

where k is the number of switches used, t

SW

is the switch delay, t

FPGA

is the FPGA

delay, m is the number of DPRAM accesses required, t

DPR

is the DPRAM access

time, and t

WIRE

is the wire delay. Depending on the type of transmission link used,

one or more terms in the equation will be eliminated. Table 4.2 shows the chan-

nel delay parameter values for different types of transmission links considered in

this work.

The delay due ...