On-Chip Communication Architectures

64 CHAPTER 3 On-Chip Communication Architecture Standards

The advantage here is that the signal need only cover the distance between

latches in a single clock cycle. Thus, by inserting register slices, timing closure

(i.e., ensuring timing requirements of a design are met) becomes relatively

easier. Introducing the register slices will of course increase the latency (in

terms of number of cycles required) for communicating on the bus. However,

the bus can now be operated at a much higher frequency (compared to a bus

with no register slices inserted) which can improve overall system perfor-

mance. AHB, in contrast, does not provide any such means ...