July 2010
Intermediate to advanced
544 pages
22h 33m
English
Content preview from On-Chip Communication Architectures
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248 CHAPTER 6 Synthesis of On-Chip Communication Architectures
[83] A. Nalamalpu and W. Burleson, “Repeater insertion in deep sub-micron CMOS: Ramp-based
analytical model and placement sensitivity analysis, ” i n Proceedings of IEEE International
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[84] S. Srinivasaraghavan and W. Burleson , “ Interconnect effort—A unifi cation of repeater inser-
tion and logical effort ,” IEEE Computer Society Annual Symposium on VLSI , 2003 , pp.
55 – 61 .
[85] L . P. P. P. van Ginneken ,
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