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On-Chip Communication Architectures
book

On-Chip Communication Architectures

by Sudeep Pasricha, Nikil Dutt
July 2010
Intermediate to advanced
544 pages
22h 33m
English
Morgan Kaufmann
Content preview from On-Chip Communication Architectures
511
Index
Bus cycle-accurate (BCA) simulation , 162
Bus cycle-accurate shell (BCASH) , 347
Bus encoding , 253
Bus expander compression scheme , 273
Bus extender scheme , 261
Bus-invert (BI) code , 262 , 263
with bus wire reordering , 276
Bus line model , 151
Bus matrix communication architectures
arbiter , 159
bus wires , 159–164
decoder , 159
input stage , 158
macro-models , 155–164
output stage , 159
Bus matrix confi gurations
decomposed power for , 178
normalized power for , 177
Bus matrix (or crossbar) topology synthesis ,
192–195
Bus protocol , 372
secur
ity support in ...
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Publisher Resources

ISBN: 9780123738929