On-Chip Communication Architectures

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CHAPTER

Over the past 10 years, the source of the critical signal delays has undergone a

major transition. With the scaling of active device feature sizes into the deep sub-

micrometer (DSM) regime, the on-chip interconnect has become the primary

bottleneck in signal fl ow within high complexity, high speed integrated circuits

(ICs). The smaller feature size in DSM technology nodes reduces the delay of the

active devices; however, the effect on delay due to the passive interconnects has

increased rapidly, as described by the 2005 International Technology Roadmap for

Semiconductors (ITRS) [1]. The transition from an IC dominated by gate dela ...