On-Chip Communication Architectures

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shown in Fig. 5.15 . A software benchmark executing on the processors generated

the traffi c on the STBus node. The SystemC simulation generated a trace fi le that

contained comprehensive print-on-change information sampled on a clock cycle

basis. This co-simulation fi le was used to drive the gate level Verilog simulation

using VCS [73], and obtain a detailed power analysis of the mapped netlist using

PowerCompiler [73]. Figure 5.16 compares the power estimated by simulating the

SystemC framework that was enhanced by the power models ( P

estimated

), with the

power measured by PowerCompiler at the gate level ( P

measured

). The system level ...