On-Chip Communication Architectures

24 CHAPTER 2 Bus-Based Communication Architectures

In an asynchronous bus, shown in Fig. 2.4 (b), no clock signal is present in the

control signals of the bus. In this case, bus synchronization occurs with the help

of a handshake protocol that uses request-acknowledgement signals to ensure that

the data transfer was completed successfully. For instance, for the example in Fig.

2.4(b) in which a master must write a data to a slave, the address ( ADDR) and data

(DATA) for the write data transfer is driven onto the bus by the master, along with

a control signal to indicate a write transaction ( WRITE). The master also asserts

the request ( REQ ...