On-Chip Communication Architectures

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loading, delays due to capacitive loads, high power dissipation, signal skew effects

due to large distances covered, and reliability issues. As performance requirements

of applications increase, higher bus clock speeds and shrinking process technol-

ogy make crosstalk and capacitive delays more signifi cant, and limit the maximum

bus clock speed achievable. To alleviate the problems faced by shared parallel

interconnects, switched parallel interconnect standards such as HyperTransport

[23] and RapidIO [24] have been proposed, which use narrow, point-to-point

connections. HyperTransport, for instance, supports narrower widths between 2

and ...