On-Chip Communication Architectures

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Section 6.6, we wrap up with a brief discussion on some of the physical and cir-

cuit level design techniques for on-chip communication architectures.

6.1 BUS TOPOLOGY SYNTHESIS

The topology of a bus-based on-chip communication architecture determines the

number of buses in the system, the manner in which they are interconnected to

each other, and how the components in the system are allocated (connected) to

the buses in the communication architecture. Synthesis approaches that attempt

to generate a bus topology must therefore determine the number of buses, their

manner of interconnection, and component allocation, while satisfying any ...