On-Chip Communication Architectures

426 CHAPTER 11 Physical Design Trends for Interconnects

11.4.5 Power Considerations

In modern integrated systems, the clock signal may drive many tens of thousands

of registers, placing a large capacitive load on the network. The combination of

a large capacitive load and a demand for higher clock frequencies has led to an

increasingly larger proportion of the total power of a system dissipated within the

clock network, in some applications much greater than 40% of the total power

[100–102] . The primary component of power dissipation in most CMOS-based

digital circuits is dynamic power. It is possible to reduce CV

2

f dynamic power by ...