On-Chip Communication Architectures

116 CHAPTER 4 Models for Performance Exploration

write( ) function calls with appropriate arguments to specify data, address, and

control information.

Figure 4.8 shows a timing diagram of a write burst of length four in an SoC

design using the AMBA AHB bus architecture. Only the most relevant signals have

been shown for clarity. A master M1 requests access to the bus in cycle 1 by

asserting the HBUSREQ_M1 signal. The arbiter receives the signal, and since there

is no contention, grants the master access to the bus by asserting the HGRANT_

M1 signal in cycle 2. The master then proceeds to set the appropriate value for

each of the control ...