On-Chip Communication Architectures

216 CHAPTER 6 Synthesis of On-Chip Communication Architectures

Pasricha et al. [166] further extended the comprehensive synthesis approach

presented above by incorporating a PVT (process, voltage, temperature) variation-

aware power estimation technique (described in Section 5.4). Incorporating PVT

variation-awareness in the system level bus matrix synthesis technique described

above resulted in a set of curves for power and energy in the trade-off graph out-

puts (instead of a single curve for power in Fig. 6.22 and energy in Fig. 6.23 ), with

each curve corresponding to a different PVT corner. This allowed for a more accu-

rate power characterization ...