On-Chip Communication Architectures

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Sections 11.3 and 11.4, respectively. A brief introduction to 3-D interconnects

is provided in Section 11.5 as a glimpse into future interconnect technologies.

Finally, some concluding remarks are offered in Section 11.6.

11.1 DSM INTERCONNECT DESIGN

The steady decrease in the feature size of semiconductor devices has enhanced cir-

cuit complexity and performance. Scaling of the lateral dimensions in planar devices,

such as MOS transistors, has produced improvements in the area, power, and speed

of the devices [12]. The specifi c characteristics of interconnects, particularly the

global lines, are degraded by current scaling trends. The ...