On-Chip Communication Architectures

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11.4.6 Summary

In this section, clock distribution timing constraints are introduced and an over-

view of clock skew in terms of the local data path delay is provided. Once an

understanding of the basic timing relationships is established, several asymmetric

and symmetric clock topologies are presented, and the benefi ts and drawbacks of

these networks are discussed. Finally, methods to minimize the power consumed

within the clock distribution network are addressed as the clock network can

consume more than 40% of the total power dissipated on-chip.

11.5 3-D INTERCONNECTS

As previously mentioned, two major effects of device scaling ...