On-Chip Communication Architectures

515

Index

Hybrid communication architecture

accuracy and effi ciency , 133

CAG generated from simulation trace , 134

performance estimation approaches , 132–138

performance estimation methodology , 133

trace generated from simulation fi rst phase of

methodology , 134

Hybrid encoding scheme , 264

HyperTransport standard , 97

I

IBM cell

MPSoC designs , 1 , 7

processor employing ring topology , 2

IBM CoreConnect DCR bus , 74

IBM CoreConnect on-chip communication

architecture standard , 12 , 44 , 64–73 , 97

device control register bus , 65 , 72–73

on-chip peripheral bus , 65 , 70–72

processor local ...