On-Chip Communication Architectures

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Figure 3.24 shows a block diagram of the PLB arbiter that handles arbitration for

up to eight masters. It consists of several components that are described below:

■ Bus control unit (BCU): This supports arbitration for masters on the PLB

bus. Each master typically drives a 2-bit signal that encodes four priority levels

(highest, high, low, lowest), indicating the priority of the request to the arbiter.

The arbiter uses this information, in conjunction with the requests from other

masters to decide which master to grant the bus access to. In case of a tie, the

arbiter provides a choice of using either a fi xed (static) priority scheme ...