VLSI Digital Signal Processing Systems: Design and Implementation

13.3    INTERLEAVED FLOOR-PLAN AND BIT-PLANE-BASED DIGITAL FILTERS

This section is concerned with efficient implementation and floor-plan techniques for bit-parallel FIR digital filters. These techniques can be adapted for implementations of IIR filters as well.

Consider the constant-coefficient FIR filtering operation

where x(n) is the input signal, and f and g are filter coefficients. Assume the signal and coefficient wordlengths to be 6 and 4 bits, respectively, and both are represented in two’s complement format.

An interleaved approach [12] for high-speed filtering is presented. The main idea behind the interleaved approach is to perform the computation and accumulation of partial products associated with f and g simultaneously, which leads to dramatic reduction in the routing complexity. Another advantage is that since the truncation is performed only at the final step, it also leads to better accuracy. The multiplication chart, based on the Baugh-Wooley algorithm, for computing the output y(n) using this interleaved approach is shown in Fig. 13.10, which is the result of interleaving of 2 parallel Baugh-Wooley multiplications. Note that only the most significant 4 bits of x(n) are considered since a 6-bit result is desired at the output.

The final interleaved architecture is shown in Fig. 13.11, where the vector merging portion is a combination of carry-ripple and carry-save ...