FIR and IIR filters are the two most basic structures used in DSP. This section considers design of bit-serial FIR and IIR digital filters with fixed constant coefficients, where the multiplications with constant coefficients are decomposed and implemented using bit-serial shifts and adds.
Consider the implementation of the FIR filter
with a signal wordlength of 8. Equation (13.16) can be rewritten in terms of shifts and adds as follows:
The word-level signal flow graph of the shift-add based FIR filter is shown in Fig. 13.24(a). Due to the presence of noncausal scaling operators, this is not a feasible design. Pipelining cutsets, shown in dashed lines in Fig. 13.24(a), can be used to delay the advance scaling operations. By placing delay elements along the cutsets and replacing the delayed scaling operators with switches, a feasible bit-level pipelined bit-serial FIR filter can be derived, as shown in Fig. 13.24(b). Note that a word-level delay is equivalent to W bit-level delays for a signal wordlength of W. Therefore, the one word delay in Fig. 13.24(a) is replaced by 8 bit-level delays in Fig. 13.24(b). The switching time instances can be derived by scheduling the bit-level computations.