VLSI Digital Signal Processing Systems: Design and Implementation

13.8    CONCLUSIONS

This chapter has presented the design of bit-level arithmetic architectures. Design of bit-parallel multipliers, including carry-ripple array, carry-save array, Baugh-Wooley, and Booth-recoded multiplications has been introduced. The two efficient layout strategies, interleaved floor-plan and bit-plane, for digital filters have been discussed. Design of bit-serial multipliers using Horner’s rule as well as using systolic mapping has been addressed. This chapter has also addressed the design methodologies for bit-level pipelined bit-serial FIR and IIR filters with constant coefficients. The CSD representation has been presented for the design of low-cost, high-speed constant multipliers. Latency reduction in serial and parallel computations using associativity and tree-height reduction has been discussed. Finally, the bit-level implementation schemes for vector-vector multiplication based on the distributed arithmetic approach has been addressed. Residue arithmetic [23], which is often used for implementation of FIR digital filters and transforms, is beyond the scope of this book.

Digit-serial architectures are also attractive for discrete wavelet transforms, where higher levels of wavelet can be implemented using smaller digit sizes [24]. For example, in a 3-level wavelet, digit-sizes W/2, W/4 and W/8 can be used for levels 1, 2, and 3, respectively. Higher levels require less computation rates and can be implemented using fewer hardware, assuming use of a single ...