January 1999
Intermediate to advanced
808 pages
19h 21m
English
Algorithmic strength reduction transformation approaches have been presented. These transformations exploit substructure sharing and reduce the number of stronger operations, possibly at the expense of increasing the number of weaker operations. Strength reduction has been applied to design fast parallel FIR filters, DCTs, and parallel rank-order filters. These architectures can reduce the area and power consumption in a VLSI implementation or reduce the iteration period in a programmable DSP implementation. Strength reduction can also be applied at numerical level to reduce the implementation complexity (see Chapter 15).
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