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Designing SOCs with Configured Cores by Steve Leibson

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5.9. Shared-Memory Topologies

A variety of system topologies employ shared memories to pass large amounts of data between processors in the system. With their many buses and memory interfaces, Xtensa and Diamond processors support a variety of such topologies. Figure 5.8 shows two processors sharing memory over a common multimaster bus. This is a simple and often-used architectural approach. Xtensa and Diamond processor cores can share memory in this manner over their main PIF buses because the PIF is designed to be a multimaster bus.

Figure 5.8. Two processors can share memory over a bus.

Sharing memory over a processors’ ...

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