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Designing SOCs with Configured Cores by Steve Leibson

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11.5. The Diamond 330HiFi audio DSP Core’s Cache Interfaces

The Diamond 330HiFi audio DSP core’s data and instruction caches store data and instructions that a program is immediately using, while the rest of the data and program reside in slower main memory—RAM, or ROM. In general, the Diamond 330HiFi audio DSP core can access instruction and data caches simultaneously, which maximizes processor bandwidth and efficiency.

The Diamond 330HiFi audio DSP incorporates a pre-configured version of the Xtensa cache controller that operates separate but asymmetric, 2-way, set-associative instruction and data caches. The instruction cache is a 2-way, set-associative, 4-Kbyte cache and the data cache is a 2-way, set-associative, 8-Kbyte cache. Note that ...

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