O'Reilly logo

Designing SOCs with Configured Cores by Steve Leibson

Stay ahead with the world's most comprehensive technology and business learning platform.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, tutorials, and more.

Start Free Trial

No credit card required

11.3. Diamond 330HiFi audio DSP Core Interfaces

As shown in Figure 11.4, the Diamond 330HiFi audio DSP core has a 64-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the one local instruction RAM, two local data RAMs, and the 2-way set-associative instruction and data caches.

Figure 11.4. The Diamond 330HiFi audio DSP core has a 64-bit implementation of the Xtensa PIF (main processor interface) bus and separate interfaces for the one local instruction RAM, two local data RAMs, and the 2-way set-associative instruction and data caches.

With Safari, you learn the way you learn best. Get unlimited access to videos, live online training, learning paths, books, interactive tutorials, and more.

Start Free Trial

No credit card required