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Designing SOCs with Configured Cores by Steve Leibson

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Chapter 14. Beyond Fixed Cores

Anything you can do, I can do better. I can do any thing better than you!

—Annie Oakley in “Annie Get Your Gun,” 1946

Because many applications just don’t run fast enough on standard embedded microprocessor cores even with an auxiliary DSP core, engineering teams have hand-coded parts of many SOC designs in Verilog or VHDL to achieve system-level performance goals. However, custom, manually-coded RTL logic takes a long time to design and longer to verify. In addition, RTL blocks can’t be easily changed once they’re designed because of verification issues, yet changes are often needed to accommodate new standards or product features.

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