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Designing SOCs with Configured Cores by Steve Leibson

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Chapter 15. The Future of SOC Design

Cost [of design] is the greatest threat to continuation of the semiconductor roadmap... Today, many design technology gaps are crises.

—ITRS:2005

We have to have major technology shifts every 10 to 12 years to keep up with silicon

—Gary Smith, Gartner Dataquest

In March, 2006, researchers at the National Nano Fab Center located at the Korea Advanced Institute of Science and Technology (KAIST) announced successful fabrication of an experimental FinFET with a gate length of 3 nm. (A finFET is a field-effect transistor with a 3D gate structure that surrounds the device’s two vertical channels on three sides.) According to the KAIST development team, achieving this milestone means that we can expect Moore’s ...

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