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Designing SOCs with Configured Cores by Steve Leibson

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9.1. The Diamond 232L: A Full-Featured CPU Core

The Diamond 232L CPU architecture contains all of the basic elements of the Xtensa ISA. It has a 32-entry general-purpose register file, a 5-stage execution pipeline, 32-bit addressing. In addition, it has a demand-paged MMU with TLB that provides advanced memory management for operating systems such as Linux. The Diamond 232L CPU core also incorporates the Diamond Series processor core software-debug stack, as shown on the left of Figure 9.1. This debug stack provides external access to the processor’s internal, software-visible state through a 5-pin IEEE 1149.1 JTAG TAP (test access port) interface and through a trace port that provides additional program-trace data. Figure 9.1 is a block diagram ...

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