The 286 implemented a different TSS structure than that defined for the post-286 processors. This is referred to as a 16-bit TSS and is not covered in this book.
All post-286 processors implement the TSS structure illustrated in Figure 10-1 on page 175. This is referred to as a 32-bit TSS. Note that the 386 and the early 486 processors did not implement the Interrupt Redirection Map. It was first implemented in the Pentium® processor and was then migrated to the later versions of the 486 processor, as well as all subsequent IA32 processors. It is described in “Efficient Handling of the INT Instruction” on page 495.
At a minimum, the TSS must include locations 00h through 67h (104d locations). This required portion consists ...