The Unabridged Pentium 4 IA32 Processor Genealogy

Built-In Self-Test (BIST) Trigger

Refer to Figure 36-4 on page 859. If the INIT# pin is sampled in the low state at the trailing-edge of RESET#, the processor will execute its internal Built-In Self-Test prior to the initiation of program fetch and execution. The duration of the BIST is processor design-specific. The processor cannot monitor transactions initiated by other FSB agents while it is executing its BIST. For this reason, the processor will continually toggle the Block Next Request (BNR#) signal for the duration of the BIST. This prevents any other FSB agent from initiating a transaction until the BIST has been completed.

Figure 36-4. The BIST Trigger

If the BIST completes successfully, EAX contains zero. If an error is incurred during ...