July 2004
Intermediate to advanced
1744 pages
35h 3m
English
Content preview from The Unabridged Pentium 4 IA32 Processor GenealogyBecome an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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The Caches
Split Cache Structure
The 486 processor implemented a unified code/data cache that was subject to contention when the instruction Prefetcher and the Execution Unit issued simultaneous requests to the cache.
Starting with the Pentium® processor, all IA32 processors implement separate code and data caches, thus eliminating the contention issue related to a unified cache.
Pentium® Code Cache
Refer to Figure 20-5 on page 477. The code or instruction cache in the P5 and the P54C versions of the Pentium® was an 8KB, 2-way set-associative, read-only cache. The cache was read-only and only implemented the SI subset of the MESI protocol. Each 4KB cache way contained 128 cache lines of 32 bytes each. There was a separate 128 entry directory ...
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