July 2004
Intermediate to advanced
1744 pages
35h 3m
English
Content preview from The Unabridged Pentium 4 IA32 Processor GenealogyBecome an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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Performance Monitoring
The Pentium® was the first IA32 processor to implement logic to log performance measurement information. All subsequent IA32 processors implement Performance Monitoring logic (but the Pentium®, P6 and Pentium® 4 implementations are not compatible with each other).
The Pentium®'s Performance Monitoring logic consisted of the following (see Figure 21-12 on page 506):
Two 40-bit performance counters implemented as MSRs (PerfCtr0 and PerfCtr1).
The 32-bit CESR (Counter Event Select Register) implemented as an MSR. This register was divided into two sets of bit fields (one set for each of the two counters):
- The 6-bit CESR[ES] (Event Select) field selected the event type to be measured. The event types are defined in Appendix ...
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