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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Performance Counters

The Performance Counter logic was first implemented in the Pentium® processor (see “Performance Monitoring” on page 505). Like the Pentium® processor, the P6 family processors implement two performance counters, but its MSR register set was implemented in a slightly different manner (see Figure 24-28 on page 607). Like the Pentium®, two 40-bit counters are implemented. Unlike the Pentium®, however, rather than using one register to control the two counters, a separate MSR is used to control each of the two counters.

Figure 24-28. P6 Processor Performance Counter Logic

Purpose of the Performance Monitoring ...

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