The description of the L1 Data Cache in this section assumes that the L1 Data Cache is virtually addressed and that each cache directory entry contains a physical page address tag. This assumption is based on the following statement from an Intel® Technology Journal article entitled Hyper-Threading Technology Architecture and Microarchitecture:
“The L1 data cache is 4-way set associative with 64-byte lines. It is a write-through cache, meaning that writes are always copied to the L2 cache. The L1 data cache is virtually addressed and physically tagged.”
The Pentium® 4 processor family's L1 Data Cache has the following major characteristics:
It is a dedicated data cache. Unlike a unified cache which caches both code ...